Substrate-dependent high-field transport and self-heating in graphene transistors

Over the last decade graphene has attracted much interest for nanoelectronic applications due to its high and symmetrical carrier mobility, and high drift velocity compared to silicon. However, when graphene is placed on insulating substrates such as SiO2 or flexible plastics, its inherent superior qualities get suppressed by the influence of the underlying substrate. Interfaces and substrate material properties have a significant impact on graphene based nano-scale devices due to the reduced dimensions and large surface-to-volume ratio. Motivated by this issue, in this work we have investigated the substrate dependence of the electrical and thermal transport in graphene field-effect transistors (GFETs). We developed a simple yet practical electro-thermal model along with extensive calibration with experimental data. Special emphasis is given to the study of high-field transport and investigation of temperature-induced effects on device performance. First, we have used this electro-thermal model to examine the scaling effect of the supporting insulator (e.g. SiO2, BN) thickness on temperature maximum (hot spot) formation. Our findings showed average and maximum temperatures of GFETs scale differently due to competing electrostatic and heat sinking effects. Self-heating in GFETs causes current degradation (up to ~10-20%) in micron-sized devices on SiO2/Si but is reduced if the supporting insulator thickness is scaled down. The transient behavior of such FETs has thermal time constants in the range of 50-250 ns, dominated by the thickness of the supporting insulator and that of device capping layers. Self-heating is also reduced in shorter channel devices, due to partial heat sinking at the contacts. Next, we investigate the effect of different supporting dielectrics such as hexagonal boron nitride (h-BN), HfO2 and SiO2 on the velocity saturation of GFETs. We examine the effects from different substrates as they each present a unique scenario due to their different (re-mote) phonons and thermal conductivities, all of which influence high-field transport in GFETs. Additionally, we studied the origins of the poor current saturation in short-channel GFETs in de-tail. We study and compare the temperature profiles generated in GFETs on different insulating materials for bottom oxide and substrate through full thermal finite element method (FEM). Ma-terials with anisotropic thermal conductivity showed significant impact in heat spreading and temperature rise in the hot-spot. We apply our findings to add a guideline for the maximum “safe” power density, e.g. in GFETs on flexible substrates such as polyimide (PI), without inducing thermal deformation; the maximum is found to be ~1.8 mW/µm2 (with 200 nm BN dielectric). Finally, we also develop a physics-based compact model based on existing literature, for GFETs with well calibration against experimental data and other finite element models. This model has been implemented into a circuit simulator like Verilog-A with a minimum number of iterations for channel potential calculation. These results shed important physical insight into the high-field and thermal profile of graphene transistors. Moreover, the electro-thermal model and results presented in this dissertation can be extended for analysis of other 2D materials beyond graphene