Physical Design for Multichip Modules

172 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993.This thesis deals with four physical design problems in the multichip module (MCM) environment: interconnect analysis, chip placement, global tree construction, and layer assignment. The emphasis is on maximizing the electrical performance, based on accurate modeling of MCM interconnect behavior. A new approach, called Reciprocal Expansion, is developed for rapidly estimating the time-domain response of lossy coupled MCM interconnect structures, and its accuracy and efficiency are demonstrated experimentally. A second-order RLC delay model is presented, which captures the effects of line resistance and inductance on signal delay. A "resistance-driven" chip placement algorithm is described, which takes interconnect resistance into account to find a placement with minimum net delays. Multilayer MCM routing is decomposed into two stages: two-dimensional global tree construction and layer assignment. An algorithm for global tree construction is presented, which attempts to minimize the number and length of stubs, while simultaneously minimizing the second-order delay. Finally, the layer assignment problem is considered. A model for the multilayer ceramic MCM environment is developed. Theoretical results on the complexity of the layer assignment problem on this model are derived, and an effective heuristic algorithm is presented. A second approach to layer assignment, based on max-cut partitioning of a net interference graph, is also studied. New techniques for constructing the interference graph based on congestion and crosstalk are presented, and algorithms for max-cut partitioning and crosstalk minimization are described.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD