Layout Synthesis of Nmos Gate-Cells

132 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1983.The NMOS Gate-Cell, a regular structure that supports gate level implementations of random logic is introduced. It is an extension of the Weinberger array, where allowing input/output terminals on all four edges resulted in an improved interconnect flexibility. Intercell routing is allowed to traverse the cells such that interconnection by abutment is achieved. The cells are implemented with AND-OR-INVERT static NMOS gates, and are based on multigrid cell models which permit controlled area changes when device sizes are adjusted to accomodate modified propagation-delay requirements.An automatic synthesis system that generates the layout of NMOS gate-cells has been designed and described. It is part of an Integrated Circuit design automation system called Arsenic where the functional description of modules are hierarchically decomposed, resulting in design entities with increasingly lower complexities. The functional and structural description is passed on to the cell generation system when the complexity allows for automated layout synthesis. The main objectives were the synthesis of correct and compact cells with fast turnaround times, windows in the automatic design flow that support designer interaction, and support of practical and fabrication process dependent constraints. The synthesis is performed in two phases; the topological phase which generates the complete topology of the cell, followed by the geometrical phase which then generates the layout elements in the form of mask rectangles. Simple heuristic algorithms were developed for these two synthesis phases.Cells with up to 7 gates with a total of 15 product-terms have been generated, reflecting the typical design problems encountered at the cell level in Arsenic. Total execution times of the most complex cells were less than 6 seconds on a VAX 11/780.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD