Optimization for advanced lithography

Lithography has always been the most critical process in integrated circuit (IC) fabrication. Below the 28 nm technology node, conventional 193 nm immersion lithography (193i) with single exposure has reached its printability limit. In order to keep up with Moore's law, a lot of advanced lithography and process techniques have been coming up in the recent decade, such as fin based multiple-gate field-effect (FinFET) transistors, electron beam lithography (EBL), self-aligned double patterning (SADP) lithography, directed self-assembly (DSA), extreme ultraviolet lithography (EUVL), etc. Each of the advanced lithography techniques has its own advantages over others, but also faces great challenges due to different process limitations. In order to adopt the advanced lithography technologies in IC fabrication, their bottlenecks must be overcome first. Due to the physical limitations, it is extremely difficult to break the bottlenecks by merely improving the fabrication processes. Instead, design-technology co-optimization (DTCO) via electronic design automation (EDA) software is a more effective way. Targeting the most promising lithography and process techniques for advanced technology nodes below 20 nm, in this thesis we study their major challenges and propose potential DTCO solutions to break the bottlenecks and improve the manufacturability. First, in the sub-20 nm technology nodes, fin based multiple-gate field-effect (FinFET) transistors show great advantages over traditional planar MOSFET transistors in high performance and low power applications. Edge device degradation is among the major challenges for the FinFET process. To avoid such degradation, dummy gates are needed on device edges, and the dummy gates have to be tied to power rails in order to avoid unconnected parasitic transistors. This requires that each dummy gate must abut at least one source node after standard cell placement. If the drain nodes at two adjacent cell boundaries abut each other, additional source nodes must be inserted in between for dummy gate power tying, which takes more placement area. We propose a detailed placement optimization strategy for the standard cell based designs. By flipping a subset of cells in a standard cell row and switching pairs of adjacent cells, the number of drain to drain abutments between adjacent cell boundaries can be optimally minimized, which saves additional source node insertion and reduces the length of the standard cell row. Second, to make logic devices manufacturable for the 16 nm technology node and beyond, designers are moving towards 1D gridded design style, where a target 1D layer can be printed by the combination of a dense line layer and a cut layer. A cut layer consists of a number of identical cut patterns, each located at the line-end of a target wire. The randomness of logic circuits will mainly affect the cut pattern distribution and introduce a major challenge fabricating 1D gridded designs. With the help of hybrid lithography, people can apply different types of processes for one single layer manufacturing such that the advantages from different technologies can be combined together to further benefit manufacturing. Targeting cut printing difficulties and hybrid lithography with EBL and 193i processes, we propose a novel algorithm to optimally assign cuts to 193i or EBL processes with proper modifications on cut distribution, in order to maximize the overall throughput. Third, SADP lithography is a leading candidate for 10 nm node lower-metal layer fabrication. Spacer-is-dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. In the SID process, due to uniform spacer deposition, the spacer shape gets rounded at convex mandrel corners, and disregarding the corner rounding issue during SID decomposition may result in severe residue artifacts on device patterns. Targeting residue artifact removal, we propose an enhanced SID decomposition flow with model-based verification. However, sometimes it is impossible to remove all artifacts through SID decomposition only. Besides that, full chip SID decomposition has been proved to be an NP-complete problem. Therefore, addressing artifact issues in the design phase (e.g., detailed routing) and producing SADP-friendly layouts become much more effective. We make a careful study on the challenges for SID-compliant detailed routing and propose a graph model to capture the decomposition violations and SID intrinsic residue issues. Then a negotiated congestion based scheme is adopted to solve the overall routing problem. Fourth, at the 7 nm technology node, DSA technology is the most promising candidate for the contact/via layer fabrication. To pattern contact holes with DSA process, guiding templates are usually printed first with conventional lithography (e.g., 193i) that has a coarser pitch resolution. Then the guiding templates will determine the DSA patterns inside and these patterns have a finer resolution than the templates. The overlay accuracy of the contact holes as well as the printability of templates may vary among different templates, and in consequence, the cost of each guiding template shape is very different from others. We first discuss the DSA-aware contact layer optimization problem in the standard cell level. Given a standard cell library, we simultaneously optimize the layouts of every cell, such that the contact layer of any cell in the library can be fully patterned by a set of guiding templates, and the total cost of the templates is minimal. Then in the full chip level, we propose a DSA-aware detailed routing algorithm that takes consideration of the constraints on feasible templates for the DSA process. We guarantee that the via layers produced by our router can be successfully patterned using feasible templates only. Finally, EUV lithography is a leading candidate beyond the 7 nm technology node. One of the challenges in EUV lithography is how to utilize defective blanks to produce valid EUV masks. One effective defect mitigation approach is to cover the defects with device patterns such that mask defect will not impact the printing on wafer. We first present an efficient layout shifting algorithm that finds an optimal location to place a single layout onto a blank such that all defects are simultaneously covered. However, in many cases, it is impossible to completely mitigate all defect impact if multiple dies are tied and moved together; hence we further explore the flexility of individual die shifting. Even with that, 100% success rate in complete defect mitigation can never be guaranteed since this also depends on the designs and defect maps. Targeting imperfect defect mitigation between one pair of design and blank, we finally develop an optimal design-blank matching strategy to match multiple designs and defective blanks simultaneously