Self-Aligned Nanotube-Phase Change Memory Device

Phase change memory is a promising candidate for the next-generation nonvolatile data storage. Unlike charge-based electronics which are susceptible to leakage at nanoscale dimensions, memory devices based on phase change materials (PCMs) appear to be more scalable, storing digital information as the crystalline or amorphous state of a material. The smallest PCM devices to date have been achieved by confining their bit either as nanowires (NWs), or by contacting the PCM with carbon nanotube (CNT) electrodes. We utilize the CNT -PCM device developed in Professor Pop’s lab as a platform to study how important device characteristics of the PCM device behave when scaled down to nanoscale. In particular, besides studying the drift phenomenon in the amorphous phase, we are mainly working on optimizing fabrication techniques to build sub-50 nm PCM nanowire devices. The size of the PCM nanowire is essential to study the scalability of the PCM devices and observe any size dependent effects on key parameters such as drift coefficient, activation energy, threshold field, crystallization temperature, etc. The width of the nanowire which is fabricated in our case is determined by the nano-trench width, which is in turn considered to be affected by four factors: input voltage bias, bias duration, background temperature and sample. The factors are studied using the principle of design of experiments (DOE) and the influence of each factor on the width of the nanowire is presented.unpublishednot peer reviewedU of I OnlyUndergraduate senior thesis not recommended for open acces