Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits

With technology scaling, the variability of device parameters continues to increase. Both performance and power consumption are quite sensitive to process parameters (PP) such as length, width, doping, and oxide thickness. As a result it is critical to predict the effect of these process variations (PV) on the future manufactured die. Guard-banding is often used to safe-guard against these variations, but it is usually too pessimistic. An alternative is to perform Monte Carlo (MC) simulation. However, this can be very computationally expensive and impractical for large circuits with multiple design iterations. Statistical static timing analysis (SSTA) has been proposed to quickly estimate the performance of a circuit under process variations (PV). Even though this has been a well studied topic, to the best of the author’s knowledge, no one has considered the impact of the statistical thermal profile during statistical analysis of the propagation delay. The first part of this work presents a SSTA tool which considers this interdependence and produces accurate timing estimation. Besides traditional silicon transistors, graphene nano-ribbon (GNR) transistors are promising candidates for future scaled technologies. They offer high-mobility and mean free path and are very robust. Because these devices are very small, the impact of PVs is expected to be very large. Unlike CMOS, the evaluation of circuit-level impact of PVs on GNR field effect transistors is in very early stages. Regardless of whether SSTA, MC simulation, or guard banding is used, a compact, parameterizable, SPICE compatible model is necessary to enable any of those approaches. For this reason, the second part of this thesis focuses on the development of such a model, its verification, and application to circuit-level simulations