Stochastic computation for energy-efficient robust ultra-low-power platforms

Next-generation ubiquitous computing promises new levels in immersion and seamless technology integration enabled through a profusion of embedded signal processing (DSP)-heavy ultra-low-power (ULP) platforms. This dissertation proposes an holistic integrated stochastic computing approach to enable the design of next-generation ULP platforms that operate dramatically closer to the limits of the achievable robustness-energy-performance envelope over a highly unreliable device fabric. Stochastic computing was shown to be an elegant design approach for energy-efficient and robust systems-on-a-chip (SoC) in superthreshold applications. This dissertation studies and extends the application of stochastic computing to the minimum-energy operating point (MEOP), which is known to occur in the subthreshold regime. Analysis, architecture and circuit-level simulations, and integrated circuit (IC) measurements in a 45-nm CMOS technology, are employed to study the stochastic-subthreshold design space. Energy savings of 28% to 54% beyond minimum achievable energy Emin at the conventional (error-free) MEOP, along with 380x to 850x increase in pre-correction error rate (pe) handling capability, are demonstrated in the presence of voltage and process variations. A stochastic computing-based biomedical processing IC is designed at the MEOP. The supply voltage of the prototype IC can be scaled to 15% below its critical (error-free) value of 0.4V, while compensating for a pe=58%, improving the heart-beat detection accuracy by 19x, and achieving 28% Emin-energy savings over conventional MEOP processors. This IC consumes 14.5 fJ/cycle/1k-gate and exhibits 4.7x better energy efficiency than the state-of-the-art while tolerating 16x more voltage variations. To further enhance system-energy efficiency, this dissertation proposes an integrated design approach for ULP platforms by jointly optimizing the design of the compute cores and the energy-delivery subsystem. Joint core architecture and DC-DC converter design techniques are proposed in order to minimize the total system energy consumption. Results show a 45.5% system-energy savings and a 2.3x improvement in the efficiency of energy-delivery subsystem over the conventional case where the system is operated at the core MEOP while ignoring DC-DC converter losses. This dissertation makes a contribution, to the portfolio of stochastic computing techniques, referred to as likelihood processing (LP). LP exploits hardware error statistics to generate reliability information or confidence level on the output bits of a compute block in a statistically optimal manner and with a low complexity. The benefits of LP are demonstrated in the design of a 45-nm discrete-cosine transform (DCT) codec, which can be employed as a hardware accelerator in a ULP platform. LP is shown to tolerate 5x to 100x greater vales of pe, and achieve 15% to 71% energy savings, when compared with existing techniques. Stochastic computing advocates an explicit characterization and processing of error statistics at the architectural/system level. To support this need, this dissertation proposes a unified framework with a generalized statistical error characterization methodology. The proposed framework and methodology are analyzed and verified for a number of 45-nm DSP kernels. Furthermore, design diversity techniques are introduced in order to engineer favorable spatially-independent error-statistics and aid the robustness and implementation of stochastic computing. The proposed design principles and demonstrated energy and robustness benefits in this dissertation can be generalized beyond ULP platforms to modern high-throughput computational platforms. This is timely, because such platforms are moving the direction of becoming a heterogenous many-core SoC. Thus, the work in this dissertation, and stochastic computing in general, can provide stochastic accelerator cores for integration with conventional cores on to such a platform