WCET-Aware Optimization of Shared Cache Partition and Bus Arbitration for Hard Real-Time Multicore Systems

In recent years, multicore processors have been receiving a significant amount of attention from avionic and automotive industries as the demand for high-end real-time applications drastically increases. However, the unpredictable worst-case timing behavior that mainly arises from shared resource contention in current multicore architectures has been the biggest stumbling block for a widespread use of multicores in hard real-time systems. A great deal of research efforts have been devoted to address the issue. Among others, the development of a new multicore architecture has emerged as an attractive solution because it is possible to eliminate the sources of unpredictable interferences in the first place, or at least to turn them into predictable ones. Accordingly, this opens a new possibility of system-level optimizations with multicore-based hard real-time systems. To address this issue, this study proposes a new perspective of WCET model called tunable WCET, in which the WCET of a task is partitioned into fixed execution time and tunable delay. Our tunable WCET model enables WCET-aware shared resource allocation/arbitration by elastically deforming the tunable delays of tasks. For this, we also propose novel shared bus arbitration and cache partitioning methods called harmonic round-robin bus scheduling and two-level cache partitioning. We present a mixed integer linear programming (MILP) formulation as the solution to the optimization problem of tunable WCETs. Our experimental results show that the proposed methods can significantly lower overall system utilization.unpublishednot peer reviewe