Functional verification and timing analysis of large digital emitter-coupled logic circuits including voltage regulators

This thesis describes the algorithms implemented in a new digital emitter-coupled logic (ECL) simulation tool called iECLSIM (Illinois ECL SIMulator). From a transistor-level description, we first partition the circuit into blocks at base nodes and voltage source nodes to exploit latency in time and space. Blocks are identified as either voltage source blocks or switching blocks automatically. The voltage source blocks are simulated at dc only to accurately calculate reference voltages.We develop two event-driven simulation methods for the switching blocks. The first simulation method, functional verification, calculates the steady-state device currents and node voltages as functions of a set of input vectors. We use a simplified Ebers-Moll transistor model to accurately calculate current sharing in emitter-coupled transistors including the effect of terminal resistances. Moreover, we recognize a wide range of circuit configurations including current sources, current mirrors, leakage resistors, series resistors, and load resistors to accurately simulate a broad class of ECL digital circuits.The second simulation method, timing analysis, calculates propagation delay and rise/fall time for the current switch and emitter follower. The current switch delay uses a linearized transistor model and Elmore's time constant. For the emitter follower rising signal, simple trial functions approximate the base and emitter voltage waveforms and are substituted into coupled differential node equations which are solved at the transition midpoint to calculate the propagation delay and rise time. For the emitter follower falling signal, the propagation delay is the sum of the emitter follower transistor turn-off time and the time to discharge the load capacitance to half the voltage swing.Comparison of iECLSIM functional verification to SPICE transient analysis shows iECLSIM calculates node voltages within 15 mV of SPICE steady-state node voltages. The iECLSIM computational cost is 1000 times lower than the SPICE cost in the analysis phase for an industrial circuit with 842 bipolar transistors. Comparison of iECLSIM timing analysis to SPICE transient analysis shows iECLSIM calculates circuit delays within 20% of SPICE-calculated delays. The iECLSIM timing analysis computational cost averages four times the iECLSIM functional verification computational cost in the analysis phase.U of I OnlyETDs are only available to UIUC Users without author permissio