Add to ORKG205 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.Turn-around time is becoming a crucial problem in integrated circuit design. Thus, Programmable Logic Arrays (PLA's) have become popular means with which to implement circuits. Their regular (i.e., matrix) structure allows for easy initial design and quick changes at later stages of design. PLA's, however, waste space, and so some method for reducing them has been sought. The SQUEEZE algorithm is used in reducing PLA's. It does not guarantee the minimality of its results, but it is able to produce near minimal results in a reasonable amount of cpu time.The thesis is divided into three main sections. First, there is an introduction to PLA's. Next there is an in-depth disc...
As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex ...
For the automated design of PLA's with a minimum size, we need computationally efficient proced...
This paper presents some results of PLA area optimizing by means of its column and row folding. A m...
205 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.Turn-around time is becoming ...
321 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1983.The switching function minimi...
This Silicon Structure Project Report documents an exploratory study of Programmable Logic Array (PL...
[[abstract]]The authors present an approach that combines logic minimization and folding for a progr...
As modern integrated circuit design pushes further into the deep submicron era, the pseudo-random de...
Typescript (photocopy).The problem of minimizing two-level AND/OR Boolean algebraic functions of n i...
The Programmable Logic Array (PLA) macro is a physical structure which simpl8es LSZ chip design whil...
[[abstract]]A new design to reduce the overhead required for a fully testable PLA is proposed. This ...
We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex prog...
[[abstract]]We propose a maximum crosstalk minimization algorithm taking logic synthesis into consid...
Graduation date: 1988Minimizing the number of product terms in a PLA implementation is a large step\...
We describe two techniques for the minimization of the area of a Programmable Logic Array (PLA). Bas...
As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex ...
For the automated design of PLA's with a minimum size, we need computationally efficient proced...
This paper presents some results of PLA area optimizing by means of its column and row folding. A m...
205 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.Turn-around time is becoming ...
321 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1983.The switching function minimi...
This Silicon Structure Project Report documents an exploratory study of Programmable Logic Array (PL...
[[abstract]]The authors present an approach that combines logic minimization and folding for a progr...
As modern integrated circuit design pushes further into the deep submicron era, the pseudo-random de...
Typescript (photocopy).The problem of minimizing two-level AND/OR Boolean algebraic functions of n i...
The Programmable Logic Array (PLA) macro is a physical structure which simpl8es LSZ chip design whil...
[[abstract]]A new design to reduce the overhead required for a fully testable PLA is proposed. This ...
We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex prog...
[[abstract]]We propose a maximum crosstalk minimization algorithm taking logic synthesis into consid...
Graduation date: 1988Minimizing the number of product terms in a PLA implementation is a large step\...
We describe two techniques for the minimization of the area of a Programmable Logic Array (PLA). Bas...
As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex ...
For the automated design of PLA's with a minimum size, we need computationally efficient proced...
This paper presents some results of PLA area optimizing by means of its column and row folding. A m...