Adaptive and integrated data cache prefetching for shared memory multiprocessors

Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems. This is even more true as the gap between processor and memory speeds continues to grow. Data prefetching has been proposed as a means of addressing the data access penalty problem. Data prefetching can be controlled by hardware, software or a combination of the two, and there are many tradeoffs associated with these different approaches. Prefetch adaptivity, which involves adapting when prefetches are issued for different data, is another important issue.In this dissertation, we present novel data prefetching techniques, and we evaluate the performance of data prefetching in a multiprocessor environment, via a detailed simulation of the memory subsystem. We first present an adaptive hardware prefetching technique that uses runtime information to decide when to generate prefetches. We show that the ideal time to issue prefetches depends on system characteristics such as available bandwidth. We next propose an integrated prefetching approach. This scheme attempts to use the best aspects of both hardware and software prefetching, so as to yield a better overall scheme. We give a detailed description of the compiler analysis necessary for integrated prefetching. The performance of integrated prefetching is compared to software and hardware prefetching, and we show the effect of adapting the scheduling of prefetches at compile time. Finally, we discuss approaches that combine integrated prefetching with the adaptive hardware prefetching technique.U of I OnlyETDs are only available to UIUC Users without author permissio