Issues in Design for Testability and Self-Test

121 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1987.This thesis presents new approaches that enhance testability at the circuit and system level, and a fault-model based aliasing analysis of signature analyzers in random testing.Past work in circuit and system level testability approaches is extended by (a) Proposing new design for testability approaches for some problems related to logic races, open faults in feedback connections, the long test time required to test counters, and nonadjacent line shorts in the OR array of a programmable logic array (PLA). The proposed redesigns aim to make testing efficient by either avoiding potential test problems or adding some test logic to the circuit in order to shorten test time. (b) Proposing a novel software technique that utilizes microprocessor instructions and data registers to implement signature analyzers and pattern generators. The software implemented test modules can be used to test the sequential behavior of a peripheral control module and to reduce test program size. (c) Proposing a generalized functional fault model for peripheral control modules. Using the functional fault model, test sequences can be derived to detect faults in a peripheral control module when its internal circuit description is unavailable.An analytical model that relates fault models to the aliasing probability of signature analyzers in the context of random testing is proposed. Multiple error vectors and parallel signature analyzers are modeled. The optimal number of random test patterns needed for fault detection and minimal aliasing is determined. This fault model based analytical approach can be applied to both primitive and nonprimitive polynomial based signature analyzers.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD