A Novel VLSI Architecture For ACS Operation In Adaptive Viterbi Decoding

Abstract-The trend in the wireless communication systemshas indicated the need to dynamically adapt communicationhardware architectures according to the run time physical environment.The adaptive Viterbi algorithm, which adaptively computesthe survivor path according to the channel environment,reduces the computation of complexity and correspondinglypower consumption greatly. In this paper, the authon presenta novel VLSI architecture of Add-Compare-Select(ACS) unit ,which is the key component of the adaptive Viterbi decoder.In the proposed scheme, the compare unit is simplified from thevariable based to constant based by employing a simple transformto the Adaptive Viterbi Algorithm. Based on the simplicity of theconstant comparison circuit, we develop a parallel approach toselect Nmez paths out of 2N,,., possible paths. The proposedtransformed architecture eliminates the need for path metricstorage unit and reduces the complexity of the comparisonoperation. The proposed ACS architecture achieves 57%, 47%and 7% improvement in power, area and speed respectivelycompared to the conventional approach. Moreover, there is a25% to 47% storage reduction in the Path Metric Unit(PMU).Keynwrds: Viterbi Algorithm(VA), Adaptive Viterbi Algorithm(AVA), ACS4 halama