A comprehensive DC and AC PBTI modeling framework for HKMG n-MOSFETs

A physics-based modeling framework is proposed to calculate the threshold voltage shift (ΔV_T) in planar High-k Metal Gate (HKMG) n-MOSFETs for positive bias temperature instability (PBTI). Overall ΔV_T is estimated using the uncorrelated contributions from the Trap Generation (TG) and the electron trapping subcomponents. The time evolution of ΔV_T, measured using an ultrafast measure-stress-measure method during DC and AC stress and after Dc stress, is predicted for different experimental conditions. The modeled TG component is verified by independent direct-current I-V method. The proposed model explains PBTI in differently processed HKMG gate stacks