Design Error Localization Using Simulation Guided Weakest Precondition

Automated design error localization is essential in debugging aids. Hardware design, like ASICs, has been evolving rapidly and getting more and more complex. The consequence is the increasing difficulty in pre-silicon debugging. There is a great need from the EDA community for a better design aid tool to automize the debugging process. Some previous studies have proposed various statistical analysis methods for bug localization, but the disadvantage of these methods are the scalability and their results depend largely on the quality of input design assertions. We propose a new bug localization method based on weakest liberal precondition. It combines the basic weakest liberal precondition computation with the guidance of a concrete execution path to increase the scalability. The experiment on an eight-entry synchronous FIFO example shows the capability of narrowing down to two lines of buggy codes after we intentionally injected a constant replacement error at the initialization stage.U of I OnlyUndergraduate senior thesis not recommended for open acces