This paper presents results on the characterization of Lateral Asymmetric Channel (LAC) thin film silicon-on-insulator (SOI) MOSFETs. These devices are compared with conventional SOI MOSFETs having uniform channel doping. The measurements have been taken for a number of channel lengths, silicon film thicknesses, and tilt angles of implantation. The aspects studied include threshold voltage roll-off, kink effect, gate induced drain leakage (GIDL) and parasitic bipolar transistor action. Measurements have been supplemented by device simulations. The LAC devices show excellent characteristics, with many advantages over the conventional devices
A study of parasitic bipolar junction transistor effects in single pocket thin film silicon-on-insul...
Silicon-on-Insulator (SOI) MOSFETs were uniquely fabricated using the epitaxial lateral overgrowth (...
Abstract—In this paper, we have systematically investigated the effect of scaling on analog performa...
This paper presents the characterization and simulation results of Lateral Asymmetric Channel (LAC) ...
This paper presents the characterization and simulation results of Lateral Asymmetric Channel (LAC) ...
In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) a...
In recent years, Silicon-On-Insulator (SOI) devices have attracted considerable attention in the are...
Lateral Asymmetric Channel (LAC) p-MOSFETs with channel lengths down to 100 nm are optimized, fabric...
An analytical model is developed for laterally asymmetric channel (graded channel (GQ design in doub...
Silicon-On-Insulator (SOI) technology, which was originally developed for military applications, is ...
Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effec...
Lateral Asymmetric Channel (LAC) MOSFETs with channel lengths down to 0.1 mu m have been fabricated ...
A device based on an asymmetric channel doping profile with the aim of reducing the inherent parasit...
In this paper, we have systematically investigated the effect of scaling on analog performance param...
This paper investigates the asymmetrical characteristics of junctions and their nearby regions in su...
A study of parasitic bipolar junction transistor effects in single pocket thin film silicon-on-insul...
Silicon-on-Insulator (SOI) MOSFETs were uniquely fabricated using the epitaxial lateral overgrowth (...
Abstract—In this paper, we have systematically investigated the effect of scaling on analog performa...
This paper presents the characterization and simulation results of Lateral Asymmetric Channel (LAC) ...
This paper presents the characterization and simulation results of Lateral Asymmetric Channel (LAC) ...
In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) a...
In recent years, Silicon-On-Insulator (SOI) devices have attracted considerable attention in the are...
Lateral Asymmetric Channel (LAC) p-MOSFETs with channel lengths down to 100 nm are optimized, fabric...
An analytical model is developed for laterally asymmetric channel (graded channel (GQ design in doub...
Silicon-On-Insulator (SOI) technology, which was originally developed for military applications, is ...
Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effec...
Lateral Asymmetric Channel (LAC) MOSFETs with channel lengths down to 0.1 mu m have been fabricated ...
A device based on an asymmetric channel doping profile with the aim of reducing the inherent parasit...
In this paper, we have systematically investigated the effect of scaling on analog performance param...
This paper investigates the asymmetrical characteristics of junctions and their nearby regions in su...
A study of parasitic bipolar junction transistor effects in single pocket thin film silicon-on-insul...
Silicon-on-Insulator (SOI) MOSFETs were uniquely fabricated using the epitaxial lateral overgrowth (...
Abstract—In this paper, we have systematically investigated the effect of scaling on analog performa...