This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all situations and specially when a line is turned off to save power. In particular, we introduce three techniques: the first one turns off the cache lines by using the coherence protocol invalidations, the second one is an implementation of a cache decay technique specific for coherent caches, the third one is a performance-optimized decay-based technique for coherent caches. Experimental results, carried out by using accurate performance/thermal/energy models, show that appreciable power savings can be achieved by properly desi...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Abstract—Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadverten...
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industr...
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching of...
Abstract—This paper evaluates several techniques to save leakage in CMP L2 caches by selectively swi...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is ...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
Future CMP designs that will integrate tens of processor cores on-chip will be constrained by area a...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
Nowadays, most computer manufacturers offer chip multiprocessors (CMPs) due to the always increasing...
Decreasing power consumption in small devices such as handhelds, cell phones and high-performance pr...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Abstract—Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadverten...
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industr...
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching of...
Abstract—This paper evaluates several techniques to save leakage in CMP L2 caches by selectively swi...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is ...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
Future CMP designs that will integrate tens of processor cores on-chip will be constrained by area a...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
Nowadays, most computer manufacturers offer chip multiprocessors (CMPs) due to the always increasing...
Decreasing power consumption in small devices such as handhelds, cell phones and high-performance pr...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Abstract—Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadverten...
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industr...