The reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor temporal locality, making conventional cache management policies inefficient. Few proposals address this problem for exclusive caches. In this paper, we propose the Reuse Detector (ReD), a new content selection mechanism for exclusive hierarchies that leverages reuse locality at the SLLC, a property that states that blocks referenced more than once are more likely to be accessed in the near future. Being placed between each L2 private cache and the SLLC, ReD prevents the insertion of blocks without reuse into the SLLC. It is designed to overcome problems affecting similar recent mechanisms (low accuracy, reduced visibility window and detector thras...
Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technol...
Energy is an increasingly important consideration in memory system design. Although caches can save ...
Architects have adopted the shared memory model that implicitly manages cache coherence and cache ca...
The reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor tempor...
In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, ba...
[EN] Multi-level buffer cache hierarchies are now commonly seen in most client/server cluster config...
Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technol...
Most chip-multiprocessors nowadays adopt a large shared last-level cache (SLLC). This paper is motiv...
Memory latency has become an important performance bottleneck in current microprocessors. This probl...
Last-Level Cache (LLC) represents the bulk of a modern CPU processor's transistor budget and is esse...
With off-chip memory access taking 100's of processor cycles, getting data to the processor in a tim...
Abstract—In modern processor systems, on-chip Last Level Caches (LLCs) are used to bridge the speed ...
International audienceRecent advances in research on compressed caches make them an attractive desig...
We introduce a novel approach to predict whether a block should be allocated in the cache or not upo...
The cache interference is found to play a critical role in optimizing cache allocation among concurr...
Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technol...
Energy is an increasingly important consideration in memory system design. Although caches can save ...
Architects have adopted the shared memory model that implicitly manages cache coherence and cache ca...
The reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor tempor...
In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, ba...
[EN] Multi-level buffer cache hierarchies are now commonly seen in most client/server cluster config...
Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technol...
Most chip-multiprocessors nowadays adopt a large shared last-level cache (SLLC). This paper is motiv...
Memory latency has become an important performance bottleneck in current microprocessors. This probl...
Last-Level Cache (LLC) represents the bulk of a modern CPU processor's transistor budget and is esse...
With off-chip memory access taking 100's of processor cycles, getting data to the processor in a tim...
Abstract—In modern processor systems, on-chip Last Level Caches (LLCs) are used to bridge the speed ...
International audienceRecent advances in research on compressed caches make them an attractive desig...
We introduce a novel approach to predict whether a block should be allocated in the cache or not upo...
The cache interference is found to play a critical role in optimizing cache allocation among concurr...
Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technol...
Energy is an increasingly important consideration in memory system design. Although caches can save ...
Architects have adopted the shared memory model that implicitly manages cache coherence and cache ca...