An approximate analysis of synchronous multiple bus

This paper presents an approximate analytic model for evaluating the performance of a loosely coupled multiprocessor architecture whose memory, organized in modules, is shared by all the processors. Each memory module (Mi) is associated with a particular processor (Pi), and it may be accessed by this processor (local access) or by any other processor (Pj,ji) through b multiple shared bussed (external access). The performance indexes used in this paper are the memory bandwith B and the delay to access a memory module. The system is evaluated for different values of p' (p'=