Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1) processors are widely used in HPC for their good performance/energy consumption and performance/cost ratios achieved sharing internal resources, like the instruction window or the physical register. Some of these processors provide the software hardware mechanisms for controlling the allocation of processor’s internal resources. In this paper, we show, for the first time, that by appropriately using these mechanisms, we are able to control the tasks speed, reducing the imbalance in parallel applications transparently to the user and, hence, reducing the total execution time...
New feature sizes provide larger number of transistors per chip that architects could use in order t...
?Signatures are on le in the Graduate School. iii Chip multiprocessors (CMPs) are becoming a popular...
There is a need to increase performance under the same power and area envelope to achieve Exascale t...
Many studies have shown that load imbalancing causes significant performance degradation in High Per...
Load imbalance cause significant performance degradation in High Performance Computing applications....
Operating systems have historically been implemented as independent layers between hardware and appl...
One of the critical factors that affect the performance of many applications is load imbalance. App...
Individual processor frequencies have reached an upper physical and practical limit. Processor desig...
Achieving faster performance without increasing power and energy consumption for computing systems i...
Nowadays many supercomputer users are dissatisfied with a long waiting time for their jobs in the su...
Multithreaded processors are now common in the industry as they offer high performance at a low cost...
As high-performance computing (HPC) systems advance towards exascale (10^18 operations per second), ...
As the microprocessor industry embraces multicore architectures, inherently parallel applications be...
In parallel iterative applications, computational efficiency is essential for addressing large probl...
Microarchitectural techniques, such as superscalar instruction issue, Out-Of-Order instruction execu...
New feature sizes provide larger number of transistors per chip that architects could use in order t...
?Signatures are on le in the Graduate School. iii Chip multiprocessors (CMPs) are becoming a popular...
There is a need to increase performance under the same power and area envelope to achieve Exascale t...
Many studies have shown that load imbalancing causes significant performance degradation in High Per...
Load imbalance cause significant performance degradation in High Performance Computing applications....
Operating systems have historically been implemented as independent layers between hardware and appl...
One of the critical factors that affect the performance of many applications is load imbalance. App...
Individual processor frequencies have reached an upper physical and practical limit. Processor desig...
Achieving faster performance without increasing power and energy consumption for computing systems i...
Nowadays many supercomputer users are dissatisfied with a long waiting time for their jobs in the su...
Multithreaded processors are now common in the industry as they offer high performance at a low cost...
As high-performance computing (HPC) systems advance towards exascale (10^18 operations per second), ...
As the microprocessor industry embraces multicore architectures, inherently parallel applications be...
In parallel iterative applications, computational efficiency is essential for addressing large probl...
Microarchitectural techniques, such as superscalar instruction issue, Out-Of-Order instruction execu...
New feature sizes provide larger number of transistors per chip that architects could use in order t...
?Signatures are on le in the Graduate School. iii Chip multiprocessors (CMPs) are becoming a popular...
There is a need to increase performance under the same power and area envelope to achieve Exascale t...