We investigate some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in performance. The basic idea is to combine different threshold voltages with different cache organizations that provide different levels of performance. Multibanked organizations in combination with different approaches to allocate data to cache banks are explored. Some of the resulting cache architectures are shown to provide a good tradeoff between power and performance.Peer Reviewe
With each technology generation we get more transistors per chip. Whilst processor frequencies have ...
The number of battery powered devices is growing significantly and these devices require energy-effi...
As we approach the era of exascale computing systems, where 1,000-core can be integrated in one die,...
We investigate some power efficient data cache designs that try to significantly reduce the cache en...
We investigate some power efficient data cache designs that try to significantly reduce the cache en...
Caches consume a significant amount of energy in modern microprocessors. To design an energy-efficie...
Abstract: Static energy dissipation in cache memories will constitute an increasingly larger portion...
International audienceModern processors are using increasingly larger sized on-chip caches. Also, wi...
Abstract. Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Part...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from ...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from e...
The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity be...
Power consumption is becoming an increasingly important component of processor design. As technology...
In this paper, we propose several different data and instruction cache configurations and analyze th...
In this paper, we propose several different data and instruction cache configurations and analyze th...
With each technology generation we get more transistors per chip. Whilst processor frequencies have ...
The number of battery powered devices is growing significantly and these devices require energy-effi...
As we approach the era of exascale computing systems, where 1,000-core can be integrated in one die,...
We investigate some power efficient data cache designs that try to significantly reduce the cache en...
We investigate some power efficient data cache designs that try to significantly reduce the cache en...
Caches consume a significant amount of energy in modern microprocessors. To design an energy-efficie...
Abstract: Static energy dissipation in cache memories will constitute an increasingly larger portion...
International audienceModern processors are using increasingly larger sized on-chip caches. Also, wi...
Abstract. Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Part...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from ...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from e...
The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity be...
Power consumption is becoming an increasingly important component of processor design. As technology...
In this paper, we propose several different data and instruction cache configurations and analyze th...
In this paper, we propose several different data and instruction cache configurations and analyze th...
With each technology generation we get more transistors per chip. Whilst processor frequencies have ...
The number of battery powered devices is growing significantly and these devices require energy-effi...
As we approach the era of exascale computing systems, where 1,000-core can be integrated in one die,...