In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and globally asynchronous locally synchronous (GALS) designs. We also present a mechanism for dynamically adapting the frequency and voltage of the frontend of the CMCD with the goal to optimize the energy-delay/sup 2/ product (ED2P). Our mechanism has minimal hardware cost, is entirely self-adjustable, does not depend on any thresholds, and achieves results close to optimal. We evaluate it on 16 SPEC 2000 applications and report 17.5% ED2P reduction on average (80% of the upper bound).Peer Reviewe
With chip temperature being a major hurdle in microprocessor design, techniques to recover the perfo...
Many multicore processors are capable of decreasing the voltage and clock frequency to save energy a...
Power consumption in clock of large high performance VLSIs can be reduced by adopting Globally Async...
In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines ...
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew...
In recent years, Globally Asynchronous Locally Synchronous (GALS) designs and dynamic voltage scalin...
Microprocessors are traditionally designed to provide "best overall" performance across a ...
Multiple clock domains is one solution to the increasing problem of propagating the clock signal acr...
Journal ArticleAs clock frequency increases and feature size decreases, clock distribution and wire...
(GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to a...
Currently, several of the high performance processors used in a PC cluster have a DVS (Dynamic Volta...
As complexity increases and gate sizes shrink for monolithic, mixed-signal integrated circuit (IC) t...
Recently, improving the energy efficiency of HPC machines has become important. As a result, interes...
Microprocessors are traditionally designed to provide “best overall” performance across a wide range...
Multiple Clock Domain processors provide an attractive solution to the increasingly challenging prob...
With chip temperature being a major hurdle in microprocessor design, techniques to recover the perfo...
Many multicore processors are capable of decreasing the voltage and clock frequency to save energy a...
Power consumption in clock of large high performance VLSIs can be reduced by adopting Globally Async...
In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines ...
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew...
In recent years, Globally Asynchronous Locally Synchronous (GALS) designs and dynamic voltage scalin...
Microprocessors are traditionally designed to provide "best overall" performance across a ...
Multiple clock domains is one solution to the increasing problem of propagating the clock signal acr...
Journal ArticleAs clock frequency increases and feature size decreases, clock distribution and wire...
(GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to a...
Currently, several of the high performance processors used in a PC cluster have a DVS (Dynamic Volta...
As complexity increases and gate sizes shrink for monolithic, mixed-signal integrated circuit (IC) t...
Recently, improving the energy efficiency of HPC machines has become important. As a result, interes...
Microprocessors are traditionally designed to provide “best overall” performance across a wide range...
Multiple Clock Domain processors provide an attractive solution to the increasingly challenging prob...
With chip temperature being a major hurdle in microprocessor design, techniques to recover the perfo...
Many multicore processors are capable of decreasing the voltage and clock frequency to save energy a...
Power consumption in clock of large high performance VLSIs can be reduced by adopting Globally Async...
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