Razor-based circuits can run faster or at a lower voltage than those designed to work at the worst case corner. However, all known implementations are prone to failures due to the non-deterministic timing behavior introduced by metastability, even in the case where sufficient time is left for resolution. This paper analyzes the causes why Razor-based circuits fail and proposes a new scheme combining the Razor principle with stoppable clocks in a GALS setting. This scheme avoids any timing failure due to metastability and does not require any checkpointing or pipeline restarting logic, other than the usual auxiliary latch to store valid data. The experiments show how the Razor principle can be extended to any generic logic circuit, and not j...
In recent years, circuit reliability in modern high-performance processors has become increasingly i...
The semiconductor industry is strategically focusing on automotive markets and significant investmen...
In nanometer regime, IC designers are struggling between sig-nificant variation effects and tight po...
Metastability causes unpredictable behavior in circuits, and can cause circuit failure. Any binary v...
Rising PVT variations at advanced process nodes make it increasingly difficult to meet aggressive pe...
Communication across unsynchronized clock domains is inherently vulnerable to metastable upsets; no ...
Process and operating condition variability creates a huge problem for current and future digital in...
Abstract—The periodic nature of the global clock in traditional synchronous designs forces circuits ...
Error containment is an important concept in fault tolerant system design, and techniques like votin...
The new technologies are giving the advance systems which are capable to perform multiple operations...
International audienceIn classical synchronous designs, supply voltage droops can be handled by acco...
Abstract—A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery...
The various modes of failure of asynchronous sequential logic circuits due to timing problems are co...
In recent years, circuit reliability in modern high-performance processors has become increasingly i...
Within this work, we apply Razor to hardware accelerators that find growing application in System-on...
In recent years, circuit reliability in modern high-performance processors has become increasingly i...
The semiconductor industry is strategically focusing on automotive markets and significant investmen...
In nanometer regime, IC designers are struggling between sig-nificant variation effects and tight po...
Metastability causes unpredictable behavior in circuits, and can cause circuit failure. Any binary v...
Rising PVT variations at advanced process nodes make it increasingly difficult to meet aggressive pe...
Communication across unsynchronized clock domains is inherently vulnerable to metastable upsets; no ...
Process and operating condition variability creates a huge problem for current and future digital in...
Abstract—The periodic nature of the global clock in traditional synchronous designs forces circuits ...
Error containment is an important concept in fault tolerant system design, and techniques like votin...
The new technologies are giving the advance systems which are capable to perform multiple operations...
International audienceIn classical synchronous designs, supply voltage droops can be handled by acco...
Abstract—A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery...
The various modes of failure of asynchronous sequential logic circuits due to timing problems are co...
In recent years, circuit reliability in modern high-performance processors has become increasingly i...
Within this work, we apply Razor to hardware accelerators that find growing application in System-on...
In recent years, circuit reliability in modern high-performance processors has become increasingly i...
The semiconductor industry is strategically focusing on automotive markets and significant investmen...
In nanometer regime, IC designers are struggling between sig-nificant variation effects and tight po...