This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging
Aging of transistors can substantially shorten the lifetime of devices in sub-nanometric technologie...
One of the fundamental challenges to the performance gain in advanced semiconductor technologyis agi...
One of the fundamental challenges to the performance gain in advanced semiconductor technologyis agi...
This work presents a test and measurement technique to monitor aging and process variation status of...
Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investi...
Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investi...
Scaling of device dimensions toward nano-scale regime has made it essential to innovate novel design...
Scaling of device dimensions toward nano-scale regime has made it essential to innovate novel design...
Process variations and device aging have a significant impact on the reliability and performance of ...
Process variations and device aging have a significant impact on the reliability and performance of...
Modern generations of CMOS technology nodes are facing critical causes of hardware reliability failu...
The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems ...
The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems ...
© 2018 Elsevier Ltd This paper proposes an appropriate method to estimate and mitigate the impact of...
As technology advances and becomes increasingly smaller in scale, it makes performance and reliabili...
Aging of transistors can substantially shorten the lifetime of devices in sub-nanometric technologie...
One of the fundamental challenges to the performance gain in advanced semiconductor technologyis agi...
One of the fundamental challenges to the performance gain in advanced semiconductor technologyis agi...
This work presents a test and measurement technique to monitor aging and process variation status of...
Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investi...
Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investi...
Scaling of device dimensions toward nano-scale regime has made it essential to innovate novel design...
Scaling of device dimensions toward nano-scale regime has made it essential to innovate novel design...
Process variations and device aging have a significant impact on the reliability and performance of ...
Process variations and device aging have a significant impact on the reliability and performance of...
Modern generations of CMOS technology nodes are facing critical causes of hardware reliability failu...
The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems ...
The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems ...
© 2018 Elsevier Ltd This paper proposes an appropriate method to estimate and mitigate the impact of...
As technology advances and becomes increasingly smaller in scale, it makes performance and reliabili...
Aging of transistors can substantially shorten the lifetime of devices in sub-nanometric technologie...
One of the fundamental challenges to the performance gain in advanced semiconductor technologyis agi...
One of the fundamental challenges to the performance gain in advanced semiconductor technologyis agi...
.jpg%3Fwidth%3D300&w=3840&q=75)
Add to ORKG