Add to ORKGRecent technology trends has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these cells is that they lose their state (i.e. value) over time, and they have to be refreshed. This paper proposes the implementation of coherent caches with DRAM cells. Furthermore, we propose to use the coherence state to tune the refresh overhead. According to our analysis, an average of up to 57% of refresh energy can be saved. Also, comparing to the caches implemented in SRAMs total energy savings are on average up to 39% depending of the refresh policy with a performance loss below 8%.Peer Reviewe
Main memory has become one of the largest contributors to overall energy consumption and offers many...
Power consumption is becoming an increasingly important component of processor design. As technology...
Abstract—Ever-growing application data footprints demand faster main memory with larger capacity. DR...
Recent technology trends has turned DRAMs into an interesting candidate to substitute traditional SR...
An effective approach to reduce the static energy consumption of large on-chip memories is to use a...
An effective approach to reduce the static energy consumption of large on-chip memories is to use a ...
A DRAM cell requires periodic refresh operations to preserve data in its leaky capacitor. Previously...
DRAM memory systems require periodic recharging to avoid loss of data from leaky capacitors. These r...
DRAM cells must be refreshed (or rewritten) periodically to maintain data integrity, and as DRAM den...
DRAM cells must be refreshed (or rewritten) periodically to maintain data integrity, and as DRAM den...
Technology projections indicate that static power will become a major concern in future generations ...
SRAM and DRAM cells have been the predominant technologies used to implement memory cells in compute...
(c) 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for...
SRAM and DRAM cells have been the predominant technologies used to implement memory cells in compute...
textContemporary DRAM systems have maintained impressive scaling by managing a careful balance betwe...
Main memory has become one of the largest contributors to overall energy consumption and offers many...
Power consumption is becoming an increasingly important component of processor design. As technology...
Abstract—Ever-growing application data footprints demand faster main memory with larger capacity. DR...
Recent technology trends has turned DRAMs into an interesting candidate to substitute traditional SR...
An effective approach to reduce the static energy consumption of large on-chip memories is to use a...
An effective approach to reduce the static energy consumption of large on-chip memories is to use a ...
A DRAM cell requires periodic refresh operations to preserve data in its leaky capacitor. Previously...
DRAM memory systems require periodic recharging to avoid loss of data from leaky capacitors. These r...
DRAM cells must be refreshed (or rewritten) periodically to maintain data integrity, and as DRAM den...
DRAM cells must be refreshed (or rewritten) periodically to maintain data integrity, and as DRAM den...
Technology projections indicate that static power will become a major concern in future generations ...
SRAM and DRAM cells have been the predominant technologies used to implement memory cells in compute...
(c) 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for...
SRAM and DRAM cells have been the predominant technologies used to implement memory cells in compute...
textContemporary DRAM systems have maintained impressive scaling by managing a careful balance betwe...
Main memory has become one of the largest contributors to overall energy consumption and offers many...
Power consumption is becoming an increasingly important component of processor design. As technology...
Abstract—Ever-growing application data footprints demand faster main memory with larger capacity. DR...