A Novel Design and Implementation of FBMC Transceiver for Low Power Applications

The complex structure of the Filter Bank Multicarrier (FBMC) communication system is the main drawback affecting the performance of the system and causes a high-power consumption. The complexity arises from using a polyphase filter bank, which consists of fast Fourier Transform/ Inverse Fast Fourier Transform (FFT/IFFT) processors and a filter bank of Finite Impulse Response (FIR) filters. This paper presents the analysis and the implementation of a new design model for FBMC transceiver in which the polyphase filter is removed completely in both transmitter and receiver and uses instead of it, a multi-level cascaded structure of FIR subfilters. The coefficients of each subfilter selected using an optimization algorithm to minimize the amplitude of sidelobes compared to the amplitude of the main lobe in the frequency response of the subfilter. The proposed design reduces the number of multiplications compared to the conventional design by 65%. The field-programmable gate array (FPGA) implementation results indicate that the proposed architecture saves 24% of resources of the FPGA board, works faster, and saves 27% of power consumption compared to conventional FBMC transceiver