Reconfigurable Instrument Access Network with a Functional Port Interface

The ever-increasing need for higher performance and more complex functionality pushes the electronics industry to find a faster and more efficient way to test and debug an Integrated Circuit (IC). Currently, the IEEE Std. 1149.1, known as Joint Test Action Group (JTAG) is considered as state of the art by the industry. JTAG is used to perform debugging and testing through Test Access Port (TAP). However, the IEEE Std. 1149.1 standard has three major drawbacks, such as: • Lack of flexibility of hardware and scalability in scheduling the access to the instruments; • Boundary Scan Definition Language (BSDL), which is part of the JTAG standard, is insufficient to describe the myriad types of instruments present in an IC; • Absence of a language to ascertain the operation of an instrument independently of its position, configuration or utilization within an IC. Therefore, the IEEE Std. 1687, also known as Internal JTAG (IJTAG), was developed to mitigate these drawbacks by offering additional features, namely: • The Segment Insertion Bit (SIB) and ScanMux control bit are introduced for dynamic reconfiguration of a boundary scan path; • Procedural Description Language (PDL) and Instrument Connectivity Language (ICL) are used to fulfill the need for interfacing and description of an on-chip instrument of variable complexity. In this thesis, we proposed Universal Asynchronous Receiver Transmitter, known as UART, as a functional port to access embedded instruments and designed IJTAG network on Xilinx Field-Programmable Gate Array (FPGA) followed by implementation of the re-targeting tool in Python programming language. Our main objective was to determine if the TAP and the associated controller can be replaced by a JTAG port interface while maintaining the same functionality. Additionally, we used data transfer as a performance metric to determine the feasibility of the UART. We explored 4 different design alternatives by building a narrative from a pure software solution to full-featured hardware solution, consequently adding new components to efficiently interpret re-targeting commands, thereby optimizing data transfer and FPGA resource utilization. Finally, we made recommendations based on results obtained, as to inclusion or exclusion of the different components.Electronic devices are typically composed of various components known as Integrated Circuits (IC) or chips that operate together to fulfill the functions of the device. ICs are in turn composed of transistors, the basic element of an electronic circuit. Rapid advances in manufacturing technology has allowed for a substantial reduction in the size of these transistors. This means that designers can afford to use more transistors to produce complex ICs. However, this level of complexity has increased the effect of errors (or bugs) and faults during the design and manufacturing process. It has also made the ICs more sensitive to external environmental factors and natural processes like aging from wear and tear. Given these challenges, facilitating constant monitoring of the various components of an electronic device for failures has become a crucial task for designers. In order to achieve this in a non-intrusive manner, a solution was developed to embed the monitoring, testing and debugging (finding and removing bugs) components into the ICs during the manufacturing process. These embedded components are referred to as on-chip instruments. Since the instruments are embedded inside a chip, additional infrastructure is required to make them accessible to the environment. This is known as the instrument access network or network in short. Work has been done to design networks that allow for non-intrusive, re-configurable instrument access in an efficient manner. However, these networks require their own dedicated interface to the environment (known as a port) that cannot be used for any other purpose. This could potentially prove problematic for designers who have access to a limited amount of resources. In this thesis, we attempt to mitigate this issue by eliminating the need for a special port by connecting the network to already existing interfaces (or a functional port) that are used to facilitate the functioning of the chip. Additionally, we also develop a control scheme based on the functional port to maintain the efficiency in terms of data exchanged between the chip and environment (known as data overhead). This means that the same functionality is maintained without the need for a dedicated port. Finally, we determine if any improvements have been made by comparing the data overhead costs between implementations with the dedicated and functional ports