Access-rate guaranteed memory controller

On-chip memory plays an important role in system-on-chip (SoCs) being in most cases the dominant part in both area and power. Additionally, it determines the overall system's speed. As a result, new memory architectures and technologies have been developed over the years in order to improve the overall system performance. This project introduces the design and implementation of a memory controller algorithm that increases the throughput while guaranteeing a fix access-rate of the memory. The work is focused on incrementing the number of read operations, i.e., being capable of performing two-read operation per clock cycle, with the use of single-port memory banks. Three different algorithms are implemented (XOR solution, Word Addition solution (WA), and Bit Addition solution (BA)) and are compared in terms of area, power and speed. Moreover, they are compared to the conventional two-port memory solution. In addition, a simple BIST (built-in self-test) engine has been implemented in order to perform a basic functionality test in memory. The BIST module is integrated into the Word Addition solution. The project concludes that the area per bit of the three solutions decreases as the size of the memory increases. However, it is by increasing the number of rows that the lowest cell area per bit values are achieved. The three solutions reduce the power and the area compared to the conventional two-port memory solution, with the XOR solution being the most area and power efficient. Even though the area and power increase between solutions is significant, when considering the memory block system (memory controller and memory banks), the overall area and power difference is negligible. Moreover, the three solutions have shown to be able to work at higher speeds than conventional 28nm SRAM. Also, the system with the integrated BIST into the memory controller has an area and power significantly smaller compared to the conventional two-port memory solution. Finally, the memory controller speed is not affected by the BIST.The ever-increasing connectivity between devices and amount of data transferred and processed in processing units implies stricter demands on memories. Because of this, during the past decades, an increasing tendency of the memory's area to the total area ratio of a processing unit has been observed. For this reason, novel techniques and architectures have been developed to produce smaller and more power efficient memories. Furthermore, memories can represent the main data-processing bottleneck. This master thesis proposes a design and implementation of a memory controller that allows multiple-access to its embedded memory without significantly increasing its area. Hence, the benefits of the memory's architecture are kept, while its utilization and data rate capabilities are enhanced. The proposed memory controller stores an additional set of values that allow recovering any data from the memory without having full access to it. Therefore, two values can be retrieved at the same time, one from the memory itself, and the other from the memory-controller additional stored data