Given the increasing performance disparity between processor speeds and memory latency, making efficient use of cache memory is more important than ever to achieve good performance in memory-bound workloads. Many modern first-level caches store instructions separately from data, making code layout and code size an important factor in the cache behavior of a program. This work investigates two methods that attempt to improve code locality, namely procedure splitting and procedure positioning, previously investigated by Pettis and Hansen. They are implemented in the open-source compiler framework LLVM to evaluate their effect on the SPEC CPU2000 benchmark suite and a benchmark run of the PostgreSQL database system. We found that our implement...
Recent studies highlight that traditional transaction processing systems utilize the micro-architect...
Commercial applications such as databases and Web servers constitute the most important market segme...
The widening gap between processor and memory speeds renders data locality optimization a very impor...
Instruction cache performance is one of the bottle-necks of processor performance. In this paper, we...
Instruction cache performance is very important for the overall performance of a computer. The place...
In the past decade, processor speed has become significantly faster than memory speed. Small, fast c...
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasing...
© 1994 ACM. In the past decade, processor speed has become significantly faster than memory speed. S...
In the past decade, processor speed has become significantly faster than memory speed. Small, fast c...
High instruction fetch bandwidth is essential for high performance in today’s wide-issue outof-order...
High instruction fetch bandwidth is essential for high performance in today’s wide-issue out-of-orde...
We explore the use of compiler optimizations, which optimize the layout of instructions in memory. T...
Abstract—Exploiting locality of reference is key to realizing high levels of performance on modern p...
The memory-processor speed gap has grown so large that in modern systems accessing the main memory r...
Commercial link : http://www.springerlink.de/ ALCHEMY/http://www.springer.comCache memories were inv...
Recent studies highlight that traditional transaction processing systems utilize the micro-architect...
Commercial applications such as databases and Web servers constitute the most important market segme...
The widening gap between processor and memory speeds renders data locality optimization a very impor...
Instruction cache performance is one of the bottle-necks of processor performance. In this paper, we...
Instruction cache performance is very important for the overall performance of a computer. The place...
In the past decade, processor speed has become significantly faster than memory speed. Small, fast c...
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasing...
© 1994 ACM. In the past decade, processor speed has become significantly faster than memory speed. S...
In the past decade, processor speed has become significantly faster than memory speed. Small, fast c...
High instruction fetch bandwidth is essential for high performance in today’s wide-issue outof-order...
High instruction fetch bandwidth is essential for high performance in today’s wide-issue out-of-orde...
We explore the use of compiler optimizations, which optimize the layout of instructions in memory. T...
Abstract—Exploiting locality of reference is key to realizing high levels of performance on modern p...
The memory-processor speed gap has grown so large that in modern systems accessing the main memory r...
Commercial link : http://www.springerlink.de/ ALCHEMY/http://www.springer.comCache memories were inv...
Recent studies highlight that traditional transaction processing systems utilize the micro-architect...
Commercial applications such as databases and Web servers constitute the most important market segme...
The widening gap between processor and memory speeds renders data locality optimization a very impor...