The impact of scaling on hot-carrier degradation and supply voltage of deep-submicron NMOS transistors

\u3cp\u3eAn experimental study of hot carrier degradation and power supply voltage scaling of deep-submicron NMOS devices is presented. Devices were optimized for processes with design rule between 2 μ m and 0.17 μ m. Charge pumping measurements showed that the lifetime based on interface state generation in the devices was determined only by I\u3csub\u3esub\u3c/sub\u3e/I\u3csub\u3ed\u3c/sub\u3e and the drain current. It did not depend on gate length, oxide thickness, and substrate doping. The lifetime (determined by shifts in the maximum linear transconductance) of the devices with minimum gate length of different processes fall on a single life in plots of tau I\u3csub\u3ed\u3c/sub\u3e versus I\u3csub\u3esub\u3c/sub\u3e/I\u3csub\u3ed\u3c/sub\u3e. This behavior can be explained by the impact of interface damage on the transistor parameters of these devices. Light emission spectra and device simulation showed that nonlocal carrier heating becomes important for devices from deep-submicron processes. As a result the power supply voltage is almost independent of design rule for the deep-submicron process (V\u3csub\u3edd\u3c/sub\u3e<or=2.5 V).\u3c/p\u3