We study conflict-free data distribution schemes in parallel memories in multiprocessor system architectures. Given a host graph G, the problem is to map the nodes of G into memory modules such that any instance of a template type T in G can be accessed without memory conflicts. A conflict occurs if two or more nodes of T are mapped to the same memory module. The mapping algorithm should: (i) be fast in terms of data access (possibly mapping each node in constant time); (ii) minimize the required number of memory modules for accessing any instance in G of the given template type; and (iii) guarantee load balancing on the modules. In this paper, we consider conflict-free access to star templates. i.e., to any node of G along with all of its ...
The paper describes a new interconnection network for massively parallel systems, referred to as sta...
Graph-structured data can be found in nearly every aspect of today's world, be it road networks, soc...
We propose a novel method of scheduling memory access on a non-blocking interconnection network that...
We study conflict-free data distribution schemes in parallel memories in multiprocessor system archi...
We study conflict-free data distribution schemes in parallel memories in multiprocessor system arc...
Techniques are developed for mapping structured data to an ensemble of parallel memory modules in a ...
We study the problem of mapping the N nodes of a data structure on M memory modules so that they can...
In this paper, we present a survey of results about the problem of mapping the N items of a data str...
International audienceRecent communication standards and storage systems (e.g. wireless access, digi...
The problem of identifying intersections between two sets of d-dimensional axis-parallel rectangles ...
International audienceRecent communication standards and storage systems uses parallel architectures...
Since the divergence between the processor speed and the memory access rate is progressively increas...
Irregular parallel algorithms pose a significant challenge for achieving high performance because of...
The problem of identifying intersections between two sets of d-dimensional axis-parallel rectangles ...
International audienceFor high throughput applications, turbo-like iterative decoders are implemente...
The paper describes a new interconnection network for massively parallel systems, referred to as sta...
Graph-structured data can be found in nearly every aspect of today's world, be it road networks, soc...
We propose a novel method of scheduling memory access on a non-blocking interconnection network that...
We study conflict-free data distribution schemes in parallel memories in multiprocessor system archi...
We study conflict-free data distribution schemes in parallel memories in multiprocessor system arc...
Techniques are developed for mapping structured data to an ensemble of parallel memory modules in a ...
We study the problem of mapping the N nodes of a data structure on M memory modules so that they can...
In this paper, we present a survey of results about the problem of mapping the N items of a data str...
International audienceRecent communication standards and storage systems (e.g. wireless access, digi...
The problem of identifying intersections between two sets of d-dimensional axis-parallel rectangles ...
International audienceRecent communication standards and storage systems uses parallel architectures...
Since the divergence between the processor speed and the memory access rate is progressively increas...
Irregular parallel algorithms pose a significant challenge for achieving high performance because of...
The problem of identifying intersections between two sets of d-dimensional axis-parallel rectangles ...
International audienceFor high throughput applications, turbo-like iterative decoders are implemente...
The paper describes a new interconnection network for massively parallel systems, referred to as sta...
Graph-structured data can be found in nearly every aspect of today's world, be it road networks, soc...
We propose a novel method of scheduling memory access on a non-blocking interconnection network that...