Analog front-end characterization of the RD53A chip

For the Phase-2 upgrade of ATLAS and CMS tracking detectors, a new pixel readout chip, with a 50\,$\mu$m $\times$ 50\,$\mu$m pixel size, is being designed in 65 nm CMOS technology by the RD53 collaboration. A large-scale demonstrator chip called RD53A, containing design variations in the pixel matrix, among which are three different analog front-ends, is now available. A dedicated program of testing and detailed characterization has been devised and carried out to qualify the three front-ends in terms of key performance parameters for the operation of a pixel detector at High Luminosity LHC.For the Phase-2 upgrade of ATLAS and CMS tracking detectors, a new pixel detector readout chip, with a 50 μm × 50 μm pixel size, is being designed in 65 nm CMOS technology by the RD53 collaboration. A large-scale demonstrator chip called RD53A, is now available. The RD53A chip was designed to withstand a total ionizing dose of 500 Mrad, to operate at thresholds below 1000 e$^-$, with a noise occupancy below 10 $^{-6}$ and to cope with a hit rate up to 3 GHz cm $^{-2}$ . It contains design variations in the pixel matrix, among which are three different analog front-ends. A dedicated program of testing and detailed characterization has been devised and carried out to qualify the three front-ends. The key performance parameters for the operation of a pixel detector at High Luminosity LHC, against which the three circuits have been evaluated, are the amount of spurious hits in the detector, caused by the noise and the late hits and the dead time driven by time-over-threshold calibration