Nanomagnetic Logic based Runtime Reconfigurable Area Efficient and High Speed Adder Design Methodology

In this study, we present a runtime reconfigurable nanomagnetic (RRN) adder design offering significant area efficiency and high-speed operations. Subsequently, it is implemented using a micromagnetic simulation tool by exploiting the reversal magnetization and energy minimization nature of the nanomagnets. We compute the carry and sum of the 1-bit full adder using only two majority gates comprising a total of 7 nanomagnets and single design layout. Consequently, the on-chip clocking schematic for the proposed RRN adder implementation for both horizontal and vertical layouts are introduced. The quantitative analysis of the required resources for higher bit adder architecture using the proposed design is performed and compared with the state-of-the-art. The proposed design methodology leads to ~86 %, ~83 % and ~93 % reduction in the number of nanomagnets, majority gates and clock cycles respectively resulting in an area-efficient and high-speed RRN adder architecture