An Ultra Low Power Subthreshold Delta Sigma Digital To Analog Converter

Abstract In the last four decades the incorporation of analog, digital and mixed-signal integrated circuits (IC) using Complementary Metal Oxide Semiconductor (CMOS) technology has been dramatically increasing and is improving almost every aspect of modern life. Furthermore, the continuous advances in CMOS Very Large System Integration (VLSI) technology allow higher integration densities and the increasing number of subsystems in a single chip results in higher speed execution and lower power consumption. Therefore, the increasing digitalization in electronic circuits across a wide range of battery-operated applications where reliability and power dissipation are critical requires Digital to Analog Converters (DACs) with higher resolution and lower power consumption. The present work analyzes the operation and response of Delta Sigma DAC at subthreshold voltage levels. At subthreshold regime, the voltage supply is far below traditional voltage levels. Additionally, subthreshold operations have the advantage over other techniques to achieve the optimum operating point per operation and thereby reduce the overall power dissipation. The Delta Sigma DAC was designed in TSMC 0.25 µm CMOS technology. The design entry was done with Virtuoso Schematic Editor and the simulations at block-level and chip-level were performed with Virtuoso Spectre Simulator, which is able to interpret and simulate SPICE netlist. Furthermore, the physical design layout was made at the symbolic level with Virtuoso Layout Suit; post-layout simulations were performed utilizing the extracted netlist of the design. The DAC was simulated with a changing digital input generated from eight ideal pulse sources, which gives the maximum power consumption case. The input frequencies and supply voltage were changing in a range from 3 KHz to 293MHz and 150mv to 2.5v respectively. The main results of the DAC are the chip area 180µm x 450µm and power consumption is 4.49 µW at 350mv. The design will be fabricated in May 2011 and experimental validation of the design will be performed by the end of the year