Fault simulation and fault modeling by I(DDQ) testing

For the past 40 years, Moore\u27s Law---which describes the unrelenting improvement in CMOS technology in terms of density, performance and cost---has withstood the test of time. The most popular formulation of the Moore\u27s law is that of the doubling of the number of transistorson integrated circuits every 18 months. As feature sizes have shrunk and design tools improved over the years, the testing of integrated circuits is gaining importance. At the present time, testing constitutes a large portion (∼30%) of the total chip cost and the trend is that test cost will continue to rise. As the result of this all are looking for a test that is good (high defect coverage), cheap (Design for-Test area and test execution time), and fast (fast test development, and market introduction). So it is very important to get defect free chips in order for a higher yield and profit. Today different fault models are being used to detect the faults. Basic fault models in digital circuits includes like stuck at fault model, bridging fault model, open fault model, delay fault model, IDDQ fault model. My research is based on IDDQ fault modeling which is a method for testing CMOS integrated circuits for the presence of manufacturing faults like bridging faults, gate oxide defects, shorts between any two of the four terminals of a transistor, partial defects (defects that effect reliability but not the logic of the circuit), some delay faults, some stuck at open faults. IDDQ testing is based on the principle that a CMOS circuit would use very little power and that in stable situation, it would draw practically nothing---just the leakage current. Many common semiconductor manufacturing faults will cause the current to increase by orders of magnitude (\u3e 10-5 Amp), which can be easily detected. This concept is being proved using the SPICE simulations of benchmark circuits that included the RLC package effects. The simulations were done that three different voltages 3.0v, 3.3v, 3.6v (nominal VDD of 3.3v and plus or minus 10%) and with three different resistive short defect of 500 ohm, 1k ohm, 5k ohm and the corresponding IDDQ current for corresponding input combinations are analyzed. In this way in addition to the three fault free circuits at three different voltages, a total of 450 faulty circuits were simulated and the current analysis is done on the results obtained. Later IDDQ-Fault Location Method according to the gate type is proved where it is possible to determine which gate type has the defects by monitoring the IDDQ currents flowing in the different gate types