Design and implementation of number representations for efficient multiplierless acceleration of convolutional neural networks

Today, computer vision (CV) problems are solved with unprecedented accuracy using convolutional neural networks (CNNs), a biologically inspired machine learning concept. However, the large computational workload of CNNs prevents their ubiquitous deployment in embedded and resource constrained systems. For this reason, many approaches for dedicated CNN hardware accelerators have recently been presented in academia, as well as in industry. A key design parameter of such accelerator systems affecting requirements on memory, bandwidth, energy, and algorithmic accuracy is the supported number representation. In this regard, previous research has indicated that neural networks are resilient to fixed-point quantization of parameters and intermediate values. The research focus of this work lies on both the design and implementation of novel number representations and the extension of corresponding quantization methods for neural networks. In particular, this thesis proposes novel concepts for avoiding hardware multipliers to increase energy and area efficiency of accelerator systems. In the first part of the thesis, previous fixed-point quantization methods are reviewed and a self-supervised extension is proposed which specifically enhances the quantization results on pre-trained neural networks. This novel method is the basis for further quantization procedures in the remainder of the thesis. In the second part, CNNs trained on small-scale classification tasks with binary or ternary valued parameters are evaluated. Furthermore, a hardware efficient method for stochastic rounding is introduced, and it is experimentally shown to enhance classification performance while avoiding the need for multiplications. The third and fourth part of the thesis are devoted to the logarithmic quantization of pre-trained CNNs for large-scale image classification and semantic scene segmentation. Logarithmic quantization allows bit-shift-based implementations of multiplications and therefore omits large multipliers in hardware. To mitigate accuracy degradation due to quantization, different log-bases are deployed and implications on hardware implementations are discussed. The resulting accuracy of logarithmically quantized CNNs on CV tasks is experimentally determined. The results reveal that particularly modern complex CNN architectures are prone to few-bit quantization. Therefore, the last part of the thesis presents a logarithmic-based number representation which allows to select the quantization resolution for weights, thereby increasing the accuracy of complex CNN architectures while allowing multiplierless processing