Experimental and modelling study on delamination risks for refinished electronic packages under hot solder dip loads

For electronic packaging engineers in the high reliability sectors such as aerospace, defense, oil & gas, etc., the use of commercial off-the-shelf components offer significant advantages due to their high availability, fast delivery time, and low cost. However, these components pose significant reliability challenges due to the risks associated with tin whisker formation and uncertainty on the long-term reliability of lead-free solders. To address these risks, the hot solder dip process is used to refinish the package by replacing lead-free solder finishes with lead-based finishes to meet the stringent packaging and assembly requirements for these sectors which are exempt from RoHS legislation. But the hot solder dip process is an extra process that exposes the package to an additional thermal load which will result in thermo-mechanical stresses that need to be properly understood and controlled. To address this challenge, a multi-disciplinary methodology combining thermo-mechanical models with “dip-to-destroy” experiments and Scanning Acoustic Microscopy has been developed to identify the risk of package material delamination for a number of package designs. Results show that the developed models can predict delamination risks for a range of imposed thermal gradients. Electronic package designs with a direct heat path from dipped terminations to internals of the package show a higher risk of overstress-induced delamination, and this failure is generally driven by the high temperature excursion above the glass transition point of the molding compound. The novelty and significance of these findings is that the derived methodology can be used by electronic packaging designers to optimize the thermal parameters of the hot-solder-dip process so that subsequent refinished packages can meet the stringent high reliability requirements for these sectors