Implementation of hardware vector floating point accelerator for RISC-V processor

Tema ovog diplomskog rada je izrada sklopovskog vektorskog akceleratora za obradu brojeva s pomičnim zarezom prema IEEE-754 standardu te njegova primjena u sustavu s RISC-V procesorom. Za sustav u koji će akcelerator biti integriran odabrana je HERO heterogena razvojna platforma zbog svoje prilagodljivosti i otvorenosti. U radu su istražena i opisana sučelja sklopovskih obradbenih jedinica (HWPE) za HERO platformu te sklopovlje i programska podrška HERO platforme. Opisana je sklopovska arhitektura i programski model akceleratora te je provedena usporedba ubrzanja u odnosu na obradu brojeva s pomičnim zarezom na RISC-V jezgrama prisutnim na HERO platformi.The topic of this thesis is implementation of hardware vector floating point accelerator according to IEEE-754 standard and its usage in a system with RISC-V processor. HERO - a heterogeneous research platform was chosen as the system in which the accelerator will be integrated because of its flexibility and openness. Hardware processing engine (HWPE) interfaces are researched and described in this thesis, as well as HERO platform hardware and software stack. The hardware architecture and programming model of the accelerator is described and a speedup comparison is made between executing the floating point operations on the accelerator as opposed to executing them on the RISC-V cores present in the HERO platform