If a test set for more complex faults than stuck-at faults is generated, higher defect coverage would be obtained. Such a test set, however, would have a large number of test vectors, and hence the test costs would go up. In this paper we propose a method to detect bridge defects with a test set initially generated for stuck-at faults in a full scan sequential circuit. The proposed method doesn\u27t add new test vectors to the test set but modifies test vectors. Therefore there are no negative impacts on test data volume and test application time. The initial fault coverage for stuck-at faults of the test set is guaranteed with modified test vectors. In this paper we focus on detecting as many as possible non-feedback AND-type, OR-type and ...
In combinational logic circuits, stuck-at faults are permanent faults that are modelled as logical p...
International audienceThe topical problem of effective verification of digital circuits of different...
The growing dispersion of ICs' parameters poses relevant uncertainties on gate output conductances...
Two approaches have been used to balance the cost of generating effective tests for IC's and th...
Precise failure analysis requires accurate fault diagnosis. A previously proposed method for diagnos...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Program year: 1997/1998Digitized from print original stored in HDRWhenever integrated circuits are m...
We describe a system for generating accurate tests for bridge faults (with or without feedback) in C...
This paper studies pseudo-random pattern testing of bridging faults. Although bridging faults are ge...
We compare the accuracy, speed and applicability to test generation of existing bridge fault modelin...
A novel algorithm for diagnosing all two-line single bridging faults in combinational circuits is pr...
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging fa...
In combinational logic circuits the generation of complete fault detection test sets requires the de...
Applications of reversible circuits can be found in the fields of low-power computation, cryptograph...
An interconnect break is a break that occurs in the inter-connect wiring, which results in logic gat...
In combinational logic circuits, stuck-at faults are permanent faults that are modelled as logical p...
International audienceThe topical problem of effective verification of digital circuits of different...
The growing dispersion of ICs' parameters poses relevant uncertainties on gate output conductances...
Two approaches have been used to balance the cost of generating effective tests for IC's and th...
Precise failure analysis requires accurate fault diagnosis. A previously proposed method for diagnos...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Program year: 1997/1998Digitized from print original stored in HDRWhenever integrated circuits are m...
We describe a system for generating accurate tests for bridge faults (with or without feedback) in C...
This paper studies pseudo-random pattern testing of bridging faults. Although bridging faults are ge...
We compare the accuracy, speed and applicability to test generation of existing bridge fault modelin...
A novel algorithm for diagnosing all two-line single bridging faults in combinational circuits is pr...
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging fa...
In combinational logic circuits the generation of complete fault detection test sets requires the de...
Applications of reversible circuits can be found in the fields of low-power computation, cryptograph...
An interconnect break is a break that occurs in the inter-connect wiring, which results in logic gat...
In combinational logic circuits, stuck-at faults are permanent faults that are modelled as logical p...
International audienceThe topical problem of effective verification of digital circuits of different...
The growing dispersion of ICs' parameters poses relevant uncertainties on gate output conductances...