A low-power microcontroller in a 40-nm CMOS using charge recycling

\u3cp\u3eA 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to V\u3csub\u3eDD\u3c/sub\u3e, while its 4-kB ROM and the 16-kB SRAM are powered from V\u3csub\u3eDD\u3c/sub\u3e to 2 V\u3csub\u3eDD\u3c/sub\u3e. Since the memory and logic will, in general, draw different supply currents, the midrail V\u3csub\u3eDD\u3c/sub\u3e is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and V\u3csub\u3eDD\u3c/sub\u3e. Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 ×. Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV.\u3c/p\u3