A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-eventrepresentation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a 2D winner-take-all chip, a delay line chip, a learning classifier chip, and a set of PCBs for computer interfacing and address space remappings. The components use a mixture of analog and digital computation and will learn to classify trajectories of a moving object. A complete experimental setup and measurements results are shown.Unión Europea IST-2001-34124 (CAVIAR)Ministerio de Ciencia y Tecnología TIC-2003-08164-C0
This paper introduces an event-driven feedforward categorization system, which takes data from a tem...
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware us...
Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory syst...
We present a neuromorphic cortical-layer processing microchip for address event representation (AER)...
This paper presents a hierarchical neuromorphic system for tracking objects. We use AER (Address Ev...
Neuro-inspired processing tries to imitate the nervous system and may resolve complex problems, suc...
Address-event-representation (AER) is a communications protocol for transferring spikes between bio-...
Neuromorphic engineering tries to mimic biology in information processing. Address-Event Representa...
We present a 32 32 pixels contrast retina microchip that provides its output as an address event rep...
Address-event-representation (AER) is a communication protocol that emulates the nervous system's ne...
Address event representation (AER) is a neuromorphic interchip communication protocol that allows fo...
this paper presents a first approach for implementations which fuse the Address-Event-Representatio...
In this paper, a chip that performs real-time image convolutions with programmable kernels of arbit...
Chicca E, Whatley AM, Lichtsteiner P, et al. A multi-chip pulse-based neuromorphic infrastructure an...
Abstract—We present a 32 32 pixels contrast retina microchip that provides its output as an address ...
This paper introduces an event-driven feedforward categorization system, which takes data from a tem...
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware us...
Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory syst...
We present a neuromorphic cortical-layer processing microchip for address event representation (AER)...
This paper presents a hierarchical neuromorphic system for tracking objects. We use AER (Address Ev...
Neuro-inspired processing tries to imitate the nervous system and may resolve complex problems, suc...
Address-event-representation (AER) is a communications protocol for transferring spikes between bio-...
Neuromorphic engineering tries to mimic biology in information processing. Address-Event Representa...
We present a 32 32 pixels contrast retina microchip that provides its output as an address event rep...
Address-event-representation (AER) is a communication protocol that emulates the nervous system's ne...
Address event representation (AER) is a neuromorphic interchip communication protocol that allows fo...
this paper presents a first approach for implementations which fuse the Address-Event-Representatio...
In this paper, a chip that performs real-time image convolutions with programmable kernels of arbit...
Chicca E, Whatley AM, Lichtsteiner P, et al. A multi-chip pulse-based neuromorphic infrastructure an...
Abstract—We present a 32 32 pixels contrast retina microchip that provides its output as an address ...
This paper introduces an event-driven feedforward categorization system, which takes data from a tem...
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware us...
Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory syst...