Investigation of Anomalous Capacitance-Voltage Behavior Caused by Interface Dipoles and the Effect of Post-Metal-Annealing

Anomalous capacitance-voltage (CV) behavior was observed in MOS devices with zirconium oxide gate dielectrics using pulse CV technique. The relative positions of up and down CV traces measured by pulse technique were opposite to those by conventional CV measurement. This unusual phenomenon cannot be inconsistently explained by charge trapping and de-trapping mechanisms. Therefore, a hypothesis related with interface dipoles was proposed. With regard to the formation of the interface dipole, it may be related to the oxygen density difference between the high-k layer and native SiOx layer. In addition, this anomaly was sensitive to growth temperature as well as post-metal-annealing process. However, after annealing in either nitrogen or forming gas ambient, the relative positions of up and down CV curves measured by the pulse technique were consistent with those obtained by conventional CV measurement