Automated delay estimation at signalized intersections : phase I concept and algorithm development.

PDFTech ReportUT-11.052676346Signalized intersectionsTraffic signal timingTravel timeUtahUtah. Dept. of TransportationSaito, MitsuruForbush, TaylorBrigham Young University. Dept. of Civil and Environmental EngineeringUtah. Dept. of Transportation. Research DivisionUS Transportation CollectionCurrently there are several methods to measure the performance of surface streets, but their capabilities in dynamically estimating vehicle delay are limited. The objective of this research is to develop a method to automate traffic delay estimation in real-time using existing field traffic data collection technologies. This research has focused on method and algorithm development that can be applied to existing technologies. Two algorithms were developed to run automatically using Microsoft Excel and Visual Basic to calculate traffic delay from data collected from existing vehicle detection. The algorithms were developed using computer modeling software to simulate different lane configurations. The lane configurations tested were through-only lanes, through lanes with a midblock driveway, and through lanes with a turning bay. Different levels of volumes were simulated for each of the lane configurations. Results were promising for each lane configuration. The through-only configuration showed excellent results with maximum errors less than 3 seconds per vehicle for each test. The through lanes with the driveways test was evaluated using added detection at the driveway locations and no detection at the driveways. Results using the driveway sensors had 93 percent of the calculated average delays with less than 5 seconds per vehicle of error. Results without the driveway sensors had 84 percent of the calculated average delays with less than 5 seconds of error. Results for the turning bay configuration had 94 percent of the calculated turning bay results with less than 5 seconds per vehicle of error. It is recommended to conduct a hardware-in-loop analysis to make certain the algorithms developed in this study perform as expected in a dynamic operation