Hardware acceleration of FPE algorithms

U sklopu ovog rada razmatraju se značajke algoritma FF1, jodnog od skupine algoritama FPE. Nakon razumijevanja načina rada funkcija šifriranja i dešifriranja algoritma FF1 pristupa se profiliranju algoritma FF1 koristeći alate Callgrind i KCachegrind u svrhu pronalaženja vremenski kritičnih dijelova implementacije algoritma FF1 preuzetu s repozitorija za praćenje verzija izvornog koda github.com/0NG/Format-Preserving-Encryption. Nakon pronalaska vremenski kritičnih dijelova pristupa se sklopovskom ubrzanju algoritma koristeći se razvojnom pločicom ZedBoard Zynq-7000. Zbog ograničenja koja su istaknuta NIST specifikacijom za algoritam FPE te sklopovlja koji se koristi, ubrzanje algoritma se ostvaruje ubrzavanjem AES šifriranja. Ubrzanje AES šifriranja ostvaruje se korištenjem implementirane AES Rijndael IP jezgre preuzete s javno dostupnog repozitorija OpenCores. Zbog korištenja AXI4-Lite protokola za prijenos podataka iz procesorske jedinice do programabilne logike te ograničenja algoritma FPE ubrzanje nije postignuto u odnosu na OpenSSL implementaciju algoritma. Navode se potencijalna rješenja kojima bi se moglo postići ubrzanje algoritma FPE. Kod postupka ubrzavanja koristili su se Xilinx alati koji pružaju mogućnosti sinteze programskog jezika C u jezik za opis sklopovlja. Alati koji su se koristili u radu su (1) Vivado HLS (2) Xilinx SDx (3) Vivado Design Suite. Postupci korištenja alata, na visokoj razini, objašnjeni su na primjeru ubrzavanja algoritma FF1.This paper offers an overview of FF1 algorithm features. FF1 algorithm is a part of the FPE algorithms group. After understanding how FF1 algorithm's encryption and decryption functions work, this paper begins with the code profiling process to find out time-critical parts of the algorithm. The tools used for profiling the code, retrieved from the versioning source control repository github.com/0NG/Format-Preserving-Encryption, are Callgrind and KCachegrind. After the time-critical bottlenecks are located in the code, the process of hardware acceleration begins. The hardware on which we accelerate the algorithm is the ZedBoard Zynq-7000. Because of the FF1 algorithm constraints, pointed out by the NIST specification, only the AES encryption is accelerated in hardware. The AES encryption is accelerated using Rijndael AES encryption IP core, an off-the-shelf component provided by OpenCore, an open source repository. For connecting the processing core with the programmable logic, the AXI4-Lite protocol is used. Because of this, the hardware-accelerated FF1 does not provide a faster implementation than the OpenSSL implementation of the FF1 algorithm. The paper offers possible solutions which are likely to result in a faster hardware implementation of the FPE algorithm. The tools used for the hardware acceleration process are: 1. Vivado HLS, 2. Xilinx SDx and 3. Vivado Design Suite. A high-level overview of how to use these tools can be applied in the process of hardware accelerating of the FPE algorithm is provided in the paper