Analyzing SEU Effects in SRAM-based FPGAs

Commercial-Off-The-Shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memory. The method combines radiation testing for technology characterization and simulation-based fault injection for SEU propagation. Experimental results we gathered with the purpose of modeling the effects of SEUs in the FPGA configuration memory are reported and commented