Journal ArticleWe introduce a simple hierarchical design technique for building high-performance self-timed components using dynamic domino-style circuits. This technique is useful for building handshaking style functional blocks and for self-timed data path components. We wrap the dynamic domino circuit in a wrapper that communicates using a request/acknowledge protocol and mediates the precharge/ evaluate cycle of the dynamic logic. We apply standard bundled delay matching for completion detection but add an early completion feature that can signal completion if function validity can be determined from the output value. The circuit overhead required for this early-acknowledge feature is relatively small, but can provide measurable ...
Intervals between data items propagating in self-timed circuits are controlled by handshake signals ...
A 8-bit non-pipeline microcontroller equipped with completion detection capability is designed by us...
This paper addresses static timing verification for sequential circuits implemented in a mix of stat...
One of the challenges of high speed digital circuit design has been to achieve timing closure. With ...
One of the challenges of high speed digital circuit design has been to achieve timing closure. With ...
This paper discusses the application of the timing analysis tool ATACS to the high performance, self...
Abstract: Reduction of propagation delay is very important for high speed applications. This paper g...
Abstract — This paper addresses static timing verification for sequential circuits implemented in a ...
Clock-delayed (CD) domino is a dynamic logic family devel-oped to provide both inverting and non-inv...
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS...
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS...
Abstract—Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook...
The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic...
We describe a high performance clocking methodology for domino pipelines. Our technique maximizes th...
[[abstract]]Factors of delay variation, such as process variation and noise effects, may cause a man...
Intervals between data items propagating in self-timed circuits are controlled by handshake signals ...
A 8-bit non-pipeline microcontroller equipped with completion detection capability is designed by us...
This paper addresses static timing verification for sequential circuits implemented in a mix of stat...
One of the challenges of high speed digital circuit design has been to achieve timing closure. With ...
One of the challenges of high speed digital circuit design has been to achieve timing closure. With ...
This paper discusses the application of the timing analysis tool ATACS to the high performance, self...
Abstract: Reduction of propagation delay is very important for high speed applications. This paper g...
Abstract — This paper addresses static timing verification for sequential circuits implemented in a ...
Clock-delayed (CD) domino is a dynamic logic family devel-oped to provide both inverting and non-inv...
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS...
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS...
Abstract—Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook...
The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic...
We describe a high performance clocking methodology for domino pipelines. Our technique maximizes th...
[[abstract]]Factors of delay variation, such as process variation and noise effects, may cause a man...
Intervals between data items propagating in self-timed circuits are controlled by handshake signals ...
A 8-bit non-pipeline microcontroller equipped with completion detection capability is designed by us...
This paper addresses static timing verification for sequential circuits implemented in a mix of stat...