MS

thesisWith the advent of aggressively scaled multicore processors utilizing increasingly complex on-chip communication architectures, the need for efficient and standardized interfaces between parallel programs and the processors that run them is paramount. Hardware designs are constantly changing. This complicates the task of evaluating innovations at all system layers. Some of the most aggressively scaled multicore devices are in the embedded domain. However, due to smaller data sets, embedded applications must be able to exploit more fine grained parallelism. Thus, more efficient communication mechanisms are needed