A New Simplified Algorithm Suitable for Implementation on FPGA for Turbo Codes

In this thesis, a new algorithm for Turbo codes and a novel implementation of turbo decoder employed with this algorithm is developed. The decoder has an optimal performance in terms of Bit Error Rate(BER) in all Signal to Noise Ratio(SNR) for all frame sizes and any states of Turbo codes. In hardware implementation, we combine the normalization and matrices modules in a single module in order to minimize the internal connection delay which is the bottleneck in hardware implementation, so that the result can be obtained in one single clock signal. Having implemented in this fashion, data rate of 28Mbps for16 state decoder has been achieved. This can be further improved by changing the algorithm for the normalization modules and LLR modules with MAX operator. The matrices modules with the proposed algorithm and the normalization and LLR modules with MAX-LOG-MAP algorithm have been implemented to achieve a data rate of 60Mbps