Model-driven reliability evaluation for MPSoC design

International audienceWhen designing a Multi-Processor System-on-Chip (MPSoC), a very large range of design alternatives arises from a huge space of possible design options and component choices. Literature proposes numerous Design-Space-Exploration (DSE) approaches which mainly focus on cost optimization. In this paper, we present a DSE approach which mainly focuses on the reliability of the whole design. This approach is based on a meta-model of Multi-Processor System-on-Chips (MPSoCs) which integrates the reliability evaluation. We develop a tool that allows designers to describe and optimize their platform based on the proposed meta-model. The results obtained for an MPSoC is presented, including the improved overall reliability of the system thanks to the automatic selection of the fault tolerance strategies for each component