FPGA Implementation of a Low Latency, Neural Network-Based Speech Enhancement Algorithm

Speech enhancement algorithms have been successfully used in many applications, such as hearing-aid devices or telecommunication systems, to improve intelligibility of degraded speech signals. State-of-the-art results in this field are currently achieved by taking advantage of neural networks and other Machine Learning techniques. Nonetheless, high computational and resource requirements of neural networks hampered their usage on mobile devices, making therefore optimization and low-cost, low-power implementation of those computational systems an attractive research field. The work herein presented analyses a speech enhancement algorithm based on a Fully-Connected Feed-Forward Neural Network, and proposes a feasible hardware implementation of it. The considered network, developed and trained by the Audio Research Group of Tampere University, Finland, expressly targets low-latency and real-time applications. After a preliminary study, a system design is proposed and discussed thoroughly in all of its parts, with particular emphasis on neural network’s implementation and parameters storage. A specific quantization and encoding model of neural network weights was in fact developed and adopted in order to reduce memory footprint and relax bandwidth requirements. Furthermore, a specific integer-multiplier module and a bit shift-based Coordinate Rotation Digital Computer (CORDIC) algorithm have been implemented to speed up neural network’s operations and still reducing computational resources needed. All modules have been tested and validated individually by means of HDL simulations and field testing on a DE2 Development and Education board by Altera, which features a Cyclone II FPGA device